1. Technical Field
The present invention is generally directed to an improved data processing device. More specifically, the present invention is directed to an apparatus and method for using electric fuses (eFuses) to store phase-locked loop (PLL) configuration data.
2. Description of Related Art
In electronics, a phase-locked loop (PLL) is a closed-loop feedback control system that maintains a generated signal in a fixed phase relationship to a reference signal. Since an integrated circuit can hold a complete phase-locked loop building block, the technique is widely used in modern electronic devices, with signal frequencies from a fraction of a cycle per second up to many gigahertz.
Phase-locked loops are used in many different types of applications including frequency synthesizers for digitally-tuned radio receivers and transmitters, demodulation of both FM and AM signals, recovery of small signals that otherwise would be lost in noise, recovery of clock timing information from a data stream, clock multipliers in microprocessors that allow internal processor elements to run faster than external connections while maintaining precise timing relationships, de-skewing of signals, bit synchronization, correcting for jitter, many different types of telecommunications applications, and the like.
For example, some data streams, especially high-speed serial data streams, (such as the raw stream of data from the magnetic head of a disk drive) are sent without an accompanying clock. The receiver may generate a clock from an approximate frequency reference, and then phase-aligns to the transitions in the data stream with a PLL. This is known as clock recovery.
As another example use of PLLs, consider that if a clock is sent in parallel with data, that clock can be used to sample the data. Because the clock must be received and amplified before it can drive the flip-flops which sample the data, there will be a finite, and process-, temperature-, and voltage-dependent delay between the detected clock edge and the received data window. This delay limits the frequency at which data can be sent. One way of eliminating this delay is to include a de-skew PLL on the receive side, so that the clock at each data flip-flop is phase-matched to the received clock.
In yet another example use of PLLs, consider that most electronic systems include processors of various sorts that operate at hundreds of megahertz. Typically, the clocks supplied to these processors come from clock generator PLLs, which multiply a lower-frequency reference clock (usually 50 or 100 MHz) up to the operating frequency of the processor. The multiplication factor can be quite large in cases where the operating frequency is multiple gigahertz and the reference crystal is just tens or hundreds of megahertz.
PLLS may be programmed with default data for controlling the operation of the PLLs. This default data is typically encoded within the PLL circuits themselves. This is a compact solution, but does not provide much flexibility. It is often necessary to change the operation of a PLL so that the PLL performs a different functionality. For example, a PLL's operation may be changed in order to perform different functions, e.g., de-skewing, clock multiplication, correcting for jitter, etc., within the same integrated circuit design, to accommodate a different design architecture, or the like. With an PLL whose default data is encoded in the PLL circuits themselves, a mask change or a metal Engineering Change (EC), i.e. changes to the manufacturing masks that affect the final metal levels of the chip, would be required to change the default values in the PLL. These are costly and time consuming processes.
Another solution is to select the default values from several internally coded choices via pins. This provides a little more flexibility to the PLL but the choices are still limited to those that are internally coded in the PLL. Moreover, this solution uses pins which are at a premium on today's devices. Pins used to select default data within a PLL may not be used to perform other, much needed, functions.
Still a further alternative solution that is more flexible is that the default data may be loaded externally, i.e. from devices external to the integrated circuit chip, at power on time. However, this solution requires additional circuitry outside the device. This results in additional cost and area usage. Furthermore, such a solution requires the use of pins to get the data on-chip. In addition, a ROM, microprocessor, or some other device external to the chip is required to provide the data.
Thus, none of the known solutions provides an adequate PLL circuit that is flexible, does not increase the cost of the circuit, and does not take up additional area than current PLL circuitry.